1. Field of the Invention
The invention relates to the field of dynamic random-access memories, particularly those employing metal-oxide-semiconductor technology.
2. Prior Art
Metal-oxide-semiconductor (MOS) memories as well as other integrated circuits are fabricated on circular silicon wafers. Several hundred identical circuits are simultaneously fabricated on a typical wafer. After processing, a probe tester tests each of the circuits on the wafer to identify operative and nonoperative circuits and in some cases partially operative circuits. Then the wafer is diced, that is, cut into a plurality of separate chips. The chips are first mounted on a lead frame and after wire bonding the lead frames are placed into integrated circuit packages.
Some manufacturers fabricate redundant columns and rows (with their associated cells) on each chip to provide replacements for faulty circuits. During probe testing or even after packaging, fuses are blown on the integrated circuit, allowing the redundant circuits to replace the faulty circuits. If a sufficient number of redundant circuits exists on a given chip for replacement of all the faulty circuits a "perfect" memory may be packaged.
It is not uncommon for an integrated circuit to pass probe testing and then after being packaged to be found inoperative. This is particularly true for dynamic random-access memories. The stress associated with packaging the integrated circuits sometimes causes them to fail. More often, however, the environmental testing conducted after packaging, (e.g., high temperature and low temperature tests) reveals deficiencies in the circuits. Unfortunately, redundancy programming is not always usable after probe testing and the circuits are discarded even though a sufficient number of redundant circuits are present within the package. The packaging of an integrated circuit particularly where a ceramic package is used is often a major component in the total cost of the integrated circuit. Consequently, the packaging of integrated circuits which fail after being packaged is significant.
As will be seen, the present invention provides additional tests at probe testing in an effort to identify those circuit elements which are likely to fail after packaging particularly from environmental testing.
Some dynamic RAMs include on-chip timing generators which initiate refresh cycles. These generators operate asynchronously with the system in which the memory is used. The memory provides a "ready" signal to indicate that data may be accessed in the memory, that is, to indicate that a refresh cycle is not about to begin or is being conducted. When the memory is to be accessed, a chip enable signal is first applied to the memory, and then if the ready signal indicates that the memory is ready, an address is coupled to the memory. A problem occurs, however, when the memory is internally processing a refresh request and before the ready signal indicates that refreshing is occurring. During this period, if the memory receives a chip enable signal, an arbitration circuit within the memory must decide whether refreshing will occur or whether accessing of the memory will be permitted. In this scheme, it is necessary to know the maximum time that can lapse between the application of a chip enable signal and the possible change of state of the ready signal. Otherwise, accessing may occur during a refresh cycle. It is difficult to test a memory to determine if this period is within specification since it is not known when the refresh request signals are occurring. As will be seen, the present invention provides a test method and apparatus which permits the testing of this critical period. The same circuitry inhibits the on-chip refreshing permitting the probe tester to more easily test the memory.
During testing, as mentioned, when defective rows or columns are found, redundant rows or columns are selected for programming. Decoders are used to select redundant circuits so that they can be programmed to recognize the addresses of the faulty rows or columns. This is described, for example, in copending application Ser. No. 320,600, filed Nov. 12, 1981 entitled "Memory Redundancy Apparatus for Single Chip Memories", which is assigned to the assignee of the present application. The present disclosure describes a simplified means for selecting redundant circuits. The described apparatus and method requires substantially fewer metal lines and thus the amount of substrate area required is reduced.